1. Field of the Invention
This invention relates generally to timing verification of synchronous digital circuits and in particular to a generalized structure with a propagation time interval and a stable time interval that is used to represent synchronous primitive elements, selected combinational elements, i.e., combinational elements with either synchronous timing behavior, or synchronous timing constraints, and external primitive elements in a synchronous digital circuit in static timing verification thereby providing a new capability in static timing verification.
2. Description of the Related Art
Digital circuits frequently include both combinational elements and synchronization elements. Combinational elements implement Boolean logic equations. A combinational element has zero or more input terminals and a single output terminal. The output signal level of a combinational element is determined solely by the present level of the input signals. Examples of combinational primitive elements include AND gates, OR gates, and inverters.
Synchronization elements typically have a clock input terminal, a data input terminal, an output terminal and up to two asynchronous control input terminals (set and reset). The output signal of a synchronization element depends not only on the present level of the input signals, but also on the past history of the input signals. Furthermore, the output signal of a synchronization element is updated only during certain time intervals which are controlled by another input signal called a clock signal. Synchronization elements include level-sensitive latches and edge-triggered flip-flops. More complex synchronization elements, such as a J-K edge triggered flip-flops, master-slave two-clock flip-flops, or a multi-bit register can be modeled as net-lists of synchronization and combinational elements.
Typically, the target technology used to implement synchronization elements imposes some timing constraints on the synchronization elements so as to ensure proper data transfer to and from the elements. In particular, the latest time the input data signal must become stable, i.e., a "set-up time," and the earliest time the input data can change again, i.e., a "hold time," are typically dictated by the target technology.
A block diagram of a typical digital system 100 that includes combinational and synchronization elements, e.g., a simple application specific integrated circuit (ASIC), is illustrated in FIG. 1. This digital system includes interface logic 101, 102, 103, clock generation circuitry 104, 105 and synchronous digital circuits 106, 107. Interface logic 101, 102, 103 is used to transport signals on and off the integrated circuit. For a purely synchronous digital circuit, interface logic 101, 102, 103 includes merely a pad and its associated logic, for example, pad protection, signal interface level adjustment, and signal conditioning logic. However, for most digital systems, at least some of the chip interface signals are asynchronous and so the interface circuit also includes asynchronous digital circuits which synchronize signals for use in digital system 100.
All periodic signals in digital system 100 are output signals of clock generation circuit 104, 105. For example, clock frequency dividers take a single fifty-percent duty cycle clock, and generate the required on-chip clock signals. Clock generation circuit 104, 105 typically includes analog components such as phase-lock loop circuits and also typically uses asynchronous logic.
Simply stated, the synchronous portion of digital system 100 is the rest of the circuitry in digital system 100. Specifically, synchronous digital circuits 106, 107 are constructed from the combinational elements and the synchronization elements described above.
Typically, in designing a digital system such as system 100, a designer provides Boolean expressions or an equivalent representation of the system and uses a computer process to generate the circuitry for the system. One problem in the design process is verification of (i) the speed characteristics and (ii) the timing characteristics of the circuitry. Timing verification looks at the time delay along all data paths within the circuit and determines whether the time delay is either too long or too short
In the simplest case, timing verification takes the specific requirements for the circuit, e.g., the system clock runs at 50 MHz, and tells the user whether the digital circuit functions correctly. In a more general timing verification, an indication of where the circuit design is failing is provided to assist the designer or automatic synthesis tool in correcting the timing failures.
Two main approaches are used for timing verification during the digital circuit design process, static timing verification and dynamic timing verification. Dynamic timing verification uses vectors provided by the designer and performs logic simulation with timing values to verify the timing behavior of the circuit. Dynamic timing verification is difficult to use because the designer must provide the input signal patterns and analyze the output wave forms to verify that the circuit functions correctly at the intended speed. Dynamic verification has the advantage that the timing behavior of any design can be analyzed and dynamic verification offers a high degree of accuracy by correctly modeling the Boolean interaction between signals.
However, the quality of the dynamic timing verification is limited by the input stimuli provided by the designer. If the designer does not correctly specify the input condition that triggers the worst-case delay path in the circuit, the dynamic timing analysis may result in an optimistic value for the circuit speed. Finally, dynamic timing verification requires extensive computer resources because a large number of input signal patterns must be simulated to offer a high degree of confidence in the results.
Static timing verification typically uses a formal analysis to verify the digital circuit timing behavior. This analysis finds the longest path in a directed acyclic graph. Static timing verification offers a more accurate picture of the digital circuit timing behavior than dynamic timing analysis because this verification implicitly considers all possible input signal patterns. However, since static timing verification ignores signal dependency in the digital circuit and considers all possible input signal patterns including signal patterns which never really occur, static timing verification timing delays may be pessimistic. Also, static timing verification is usually not applicable to all digital designs, e.g., asynchronous circuits.
Static timing verification has traditionally been limited to so called synchronous designs and even then to a limited subset of what a designer considers to be a synchronous design. Specifically, only circuit elements which can be accurately represented by one of the ideal elements that are available in the static verification system can be reliably characterized in the static timing verification. For example, if the static timing verification system includes only an ideal positive edge triggered D-type flip-flop and an ideal positive level sensitive D-type latch, only these two synchronous elements and other synchronous elements that can be accurately represented using these two ideal synchronous elements can be accurately processed by the static timing verification. Further limitations of this approach are discussed below.
While static timing verification may provide superior results with more limited resources in comparison to dynamic timing verification, static timing verification is typically considered difficult to use. The complexity of static timing verification is further demonstrated by first considering the operation of synchronization elements in more detail.
In synchronous digital circuit design, latches and flip-flops under the control of global clocks are used to synchronize signals and sequence the computation of the signals. For example, FIG. 2 is a block diagram of a positive edge-triggered D-type flip-flop 200 with a data input terminal "d", a data output terminal "q", and a clock terminal "c". Flip-flop 200 transmits the input data signal on data input terminal "d" to data output terminal "q" under the control of the clock signal on clock terminal "c". Specifically, the transmission occurs around the rising edge of the clock signal and so flip-flop 200 is referred to as a "positive edge triggered flip-flop."
To assure proper operation of flip-flop 200, the input signal on data input terminal "d" must be stable a short time before the initiation of the rising clock edge. This requirement is referred to as the "setup requirement." In addition, the input signal must remain stable for a short time after the initiation of the rising clock edge. This requirement is referred to as the "hold requirement." The signal on output terminal "q" is not guaranteed valid until after the hold requirement, sometimes referred to as the "hold time".
When the setup and hold requirements are met, the data signal is said to be "synchronized" by flip-flop 200 at the rising edge of the clock signal. Thus, the timing constraints associated with flip-flop 200 are:
(i) a specific edge of the clock signal; PA1 (ii) a setup requirement and the associated clock edge; and PA1 (iii) a hold requirement and the associated clock edge. PA1 (i) an interval of time during which data can propagate from the input data terminal to the output data terminal; PA1 (ii) a setup requirement and the associated clock edge; and PA1 (iii) a hold requirement and the associated clock edge.
In some cases, signals are not synchronized to a clock edge, but rather to a time interval. A block diagram of a device 300 that synchronizes signals to a time interval, a positive level-sensitive D-type latch, is illustrated in FIG. 3. Latch 300 also has a data input terminal "d", a data output terminal "q", and a clock terminal "c", which is typically referred to as an "enable" terminal. However, unlike flip-flop 200, latch 300 allows the input data signal on input terminal "d" to propagate to output terminal "q" any time the signal on clock terminal "c" is active, e.g., high, which is the basis for the name "positive-level sensitive latch."
When the clock signal on clock terminal "c" goes low, the output signal on terminal "q" remains at the level just before the initiation of the falling clock edge. Thus, to ensure proper operation of latch 300, the input data signal must be stable a short time before a falling clock edge, the "setup requirement", and the input data signal must remain stable until a short time after the falling clock edge, the "hold requirement". The signal on output terminal "q" is not guaranteed valid until after the hold requirement, sometimes referred to as the "hold time".
When the setup and hold requirements are met, the data signal is said to be "synchronized" by latch 300 to an interval of time. Thus, the timing constraints associated with latch 300 are:
A static timing verification system is a computer based process to which a circuit designer supplies a synchronous digital circuit. This computer process analyzes the timing characteristics of the synchronous digital circuit for all possible input signals to the circuit. The goal of static timing verification system is to assure that signals are transmitted properly in the synchronous digital circuit, or to provide an indication of where the circuit may fail so as to guide the designer in correcting the timing failure.
Specifically, the static timing verification system analyzes each data path in the synchronous digital circuit. A typical data path starts at the data output terminal of a synchronization element and ends at the data input terminal of another synchronization element. FIG. 4 is a representation of one data path. Latches 400A, 400B, and 400C each generate an output signal to combinational logic circuit 410 which in turn generates an input signal to latch 400D. Other data paths start, for example, either (i) at an input port and end at the data input terminal of a synchronization element, or (ii) at the data output terminal of a synchronization element and end at an output port, or (iii) at an input port and end at an output port.
In the static timing verification system, the designer-specific synchronous digital circuit behavior is reduced to (i) when the output signals of ideal latches 400A, 400B, and 400C are stable, i.e., after the hold times for the corresponding physical synchronous latches in the designer's circuit, and (ii) when the signal at the input terminal of ideal latch 400D is required to be stable, i.e., before the setup time of the physical synchronous latch corresponding to ideal latch 400D in the designer's circuit. Such requirements are generally called "timing constraints." The static timing verification system makes sure that all such timing constraints are met or reports why a particular constraint can not be met and by how much. Thus, the static timing verification system is a computer process that analyzes the timing characteristics of a synchronous digital circuit without requiring the time and expense of building the actual circuit and performing timing tests.
For a static timing verification system to be useful for a wide variety of digital circuits, the static timing verification system designer must anticipate all circuit elements in users' synchronous digital circuits for which the static timing verification system will be used as well as special conditions in the users' synchronous digital circuits that affect the timing characteristics. The static timing verification system designer must provide in the static timing verification system a way to convert each circuit element to a corresponding ideal element. There are two problems with this approach.
First, the designer must anticipate all types of synchronous elements and must modify the static timing verification system whenever a new synchronous element is introduced. Since the static timing verification system is a computer process that is controlled by software, this typically results in unstable software, and possible erroneous interpretation of the synchronous behavior of the new synchronous element.
Second, there are some circuit elements that can not be represented by the set of ideal synchronous elements that are typically used in a static timing verification system. Thus, the current practice in static timing verification leads to erroneous results when a new circuit element is not properly incorporated into the static timing verification system. In some cases, a user's synchronous digital circuit may not be amendable to static timing verification because the set of ideal synchronous circuit elements provided cannot be used to represent one or more circuit elements in the user's circuit.
Typically, correct and accurate static timing verification for (i) combination elements with synchronous timing behavior, such as clocked-gates and gated-clocks, (ii) external primitive elements, such as input ports and output ports, and (iii) other synchronous primitive elements, such as random-access memory(RAM), read-only memory(ROM), is not considered in most references that discuss static timing verification. However, if circuit elements such as these are not treated properly, the results of the static timing verification are at best questionable. For this reason, despite all the benefits of static timing verification, the consensus opinion is generally that dynamic timing verification is the best way to obtain accurate reliable results timing results.